Design And Implementation Of Embedded Dual-Stack Based FPGA

With the combination of embedded system with network, the ability of embedded devices to support communicating in network is absolutely necessay. For lack of enough address space, IPv4has far behind the demand of address number of devices with large number. So it is one of the significant trends to enabling embedded devices to support the next generation network. However, Internet with IPv4has considerable scale of applications, which are widely used in the whole network. It requires a transition period, during which we should solve the problem of interconnection between IPv4and IPv6. IETF proposed three types of solutions to handle the transition:Tunnel, Dual-stack and Network Address Translation. The Dual-stack method means all the hosts and routers run protocol of IPv4and IPv6together, and this solution is considered to the most effective one to handle the interconnection of IPv4and IPv6.With the upgrading of hardware performance of embedded devices, and the increasement of requirements in real-time by applications, it is necessary to accelerate the analysis of protocol. In the process of analyzing IPv6, process of filed checking and lookup of table are common. So the speed of analyzing protocol will be improved greatly by implementing these processes in hardware. Although it will be hard to verify the acceleration by solidating the whloe protocol, FPGA can be an appropriate way to check the acceleration.This paper designed and implemented a reduced embedded IPv6stack. This stack takes the same architecture of popular embedded stack-LwIP, and devided to four layers according to related RFC, which are application layer, transfer layer, network layer and link layer. It is implemented according to related standard making by IETF to be suitable for real network. Considering the limitation of embedded devices’resource, this paper reduced some functions of IPv6. The reduced stack covers most basic funtion of IPv6, such as Address Configuration, Packet Sent and Rececption, Reouter Requestion, Error Handle and so on. In the other hand, the code size and memory consumption of reduced stack are statisfied to the limitation of embedded devices.As to support communicating in IPv4, this paper integrates the above IPv6stack with LwIP to an IPv4/IPv6dual-stack. The integrated stack processes the common API layer, TCP layer and Interface Abstraction layer, but has two different network layers. This architecture makes the integrated dual-stack be tidy in code size. In the integration, modularization and independentization is fully considered. It enables IPv4to run independently with IPv6, and dual-stack to reduce to a single stack by closing the pre-compiler.Although our IPv6stack is cut and optimized, it is time-consuming for embedded devices with limited resource to resolve IPv6. This paper translates some frequent procedures in resolving to Verilog language, which can be recognized and ran in hardware. The acceleration is verified by FPGA, and the experiment shows the effect is significant. For the limitation of technique and time, verifying by putting the accelerated modules in whole protocol is without realizing. However, it is believed that embedded network will benefit the method of accelerating by hardware.