| Floating point arithmetic is widely used in signal processing and high-performance computing scenarios due to its wide dynamic range and high precision. Traditional Floating-point hardware design has low energy e?ciency for precision requirement of speci?c application. Nowadays the demands for power saving and performance e?-ciency are increasingly high. Therefore developing precision variable and hardware reused ?oating-point unit is signi?cance in theory and practice.The main purpose of this thesis is to decrease the power consumption and increase the ?oating-point operation performance by reducing the precision redundancy and sharing hardware data path. Firstly a precision tracking model has be built based on Precision Arithmetic to guarantee the decreased precision can be satis?ed for the certain applications and scenarios. Then a precision variable multi-way Fused Multiply Add unit, which supports 1-way 24-bit, 2-way 12-bit or 4-way 6-bit variable precision?oating-point operation, has been designed. Both hardware resource and power consumption could be saved while bit width of variables decreases.The design has been synthesized in TSMC 90 nm CMOS technology, the design can operate at a frequency of 200 MHz and required area could be as small as 0.06mm2.The energy e?ciency could be as high as 546.08MFLOPS/W which achieves 3x increases while just has less than 40% area overhead. The results showed that the proposed precision variable multi-way ?oating-point unit can achieve higher ?oating-point performance under the same power consumption comparing with the traditional designs. |
