True Number Generator IC Design

The21st century with the rapid development of computer and communication technology, information security becomes increasingly important. Cryptography is a very effective technique to solve the problem of information security. An important source of security of modern cryptography is to generate the randomness of the random number of confidential data. Now widely used pseudo-random number generator, it produces the principle of random numbers using mathematical algorithms to get "random number". Pseudo-random number generator is characterized by simple structure, less occupied by hardware resources, speed, but its randomness. Once the "seed" was stolen, then its output sequence is not random. so it can not be used in the system of high security requirements such as:banking system, security chip.True Random Number Generator is able to generate true random number that can not be predicted, because the use of physical processes in a variety of random noise, such as:thermal noise, flicker noise. The main goal of paper is to design a module to meet the safety requirements on the IC.The main idea of the true random number generator sub-module design: the slow jitter oscillator sampling high-speed oscillator to generate the random sequence, and then use the XOR chain to eliminate the bias of the sequence to get the random sequence of "0" and "1" Uniform distribution. At last random number stored in the FIFO. In order to prevent the attacker uses probes to detect access to sensitive information in the chip and improve the security level of the chip, anti-tamper circuit is designed in this random number generator. When the probe exposed to anti-tamper network, the random number generator will be powered off and clear the random numbers stroed in FIFO. To reduce the overall power consumption clock gating is used in the design.The design is divided into analog and digital sections, The main part of analog is oscillator, and the remaining are the digital. The EDA tool of Automatic placement and routing we used is sysnopsys’s IC Compiler. And the GDSII generated by IC compiler is run LVS and DRC verification by Mentor Calibre. After successful verification, the entire design of the true Random Number Generator finished. This design uses the HJTC0.18um CMOS process to achieve.