High Voltage Low Power Ldmos Research

There is a super-linear relationship of Ronsp∝BV2.5between the specific on-resistance (Ron.sp) and breakdown voltage (BV) for lateral power devices, the trade-off between Ron,sp and BV is thus the main issue for power MOSFETs. To improve the relationship between Ron,sp and BV, three new device structures are proposed.(1) An ultra-low specific on-resistance (Ron.sP) silicon-on-insulator (SOI) double trenchs and double gates MOSFET (SOI DTDG MOSFET) is proposed. The MOSFET features double trenches and double polysilicon gates. Firstly, the oxide trench between source and drain not only folds the drift region, but also modulates the electric field, thereby increases the breakdown voltage (BV). Secondly, the double gates reduce Ron.sp by forming dual conduction channels. BV of93V and Ron.sp of51.8mΩ·mm2are obtained for the SOI DTDG MOSFET with3μm half-cell pitch. Compared with the SOI trench gate MOSFET (SOI TG MOSFET) and the SOI double trenches MOSFET (SOI DT MOSFET), Ron.sp of the SOI DTDG MOSFET decreases by63.3%and33.8%at the same BV, respectively.(2) A high voltage SOI LDMOS with buried n-islands is proposed. In high voltage blocking state, the ionized donors in the depleted n-islands make the electric field in the n-islands monotonously increase, leading to an increase of the electric field in the buried oxide layer. Furthermore, the holes accumulation layer in the lateral gaps of n-islands maintains the high electric field in the buried oxide layer. BV is thereby enhanced. Because the isolation effect among n-type drift region, p-type SOI layer, discontinuous n-islands is very good, there is no need to use deep trench dielectric isolation in the power Integrated Circuits. A673V buried n-islands LDMOS in a self-isolation SOI HVIC is realized on a20um SOI layer over4μm BOX. Compared with conventional LDMOS, BV of the LDMOS with buried n-islands increases by38.2%.(3) A high voltage LDMOS on Partial Silicon-On-Insulator (PSOI) with a Variable k dielectric (VK) buried layer and a buried p-layer (BP) is proposed (VK BPSOI). The variable k dielectric enhances electric field strength of the buried layer and the Si window makes the substrate share the voltage drop, the average electric field in the vertical is enhanced; the electric field peaks are introduced at the interfaces of the buried p-layer, Si window, the variable k buried layer, which modulates the electric field distribution in the lateral direction. Thus, the breakdown voltage is increased. Owing to the assistant depletion effect of the buried p-layer, the concentration of n-type drift region is increased and the specific on resistance is thus reduced. The Si window alleviates the inherent self-heating effect(SHE) in SOI device. Compared with the conventional PSOI, BV of VK BPSOI increases by43.6%and Ron.sp of VK BPSOI decreases by19%.The breakdown voltage mechanism and some important device structureal parameters are analyzed with2D simulation software MEDICI and TSUPREM4, and some feasible processes are established. Cooperating with the domestic XX reseach institution, the layout is finished, and the chip samples is tested and analyzed.