210 V Line Soi Technology Pdp Driver Chip Esd Protection Design

Up to now, plasma panel display (PDP) have become one of the most popular products, due to it’s excellent display effect. But now, the major factor that limits the popularity of PDP display equipment is the high cost of manufacture. And that, the cost of PDP driver chip can take up to20%of the whole equipment cost. So, it is important to insure the reliablility of PDP driver chip. The electro-static discharge (ESD) phenomenon is a majoy threat to PDP driver chip. The missions of this paper are studying ESD in power ICs, and designing a feasible ESD protection scheme of the PDP drive chip.In this paper, working performance and characters of high voltage devices under ESD condition were modeled and analyzed, including HV DIODE, LDNMOS and LIGBT. Then, simulation and optimization of devices had been done for better ESD robustness. After the optimization of devices, the layout design of ESD was proposed. Some ESD device’s layout design problem and the whole-chip ESD protection net scheme was introduced.Last, the chip taking ESD devices and whole-chip ESD protection net circuit was fabricated.Transmission line pulse (TLP) test was done on the fabricated chips. These test results show that the trigger voltage of ESD devices under TLP test condition would drop, and there is no snapback happened about LDNMOS and LIGBT. So, the latch-up effect can be suppressed efficiently. The PDP driver chip have achieved excellent ESD robustness, which can be attributed to devices’good performance and reasonable layout scheme. The PDP driver chip has passed±8KV Human-Body Model (HBM) ESD test with HV diode as ESD protect device. This result fully satisfies the PDP drive chip applications.