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Cpri Wan Zhao Ethernet Packet Transmission Hardware Design And Implementation

Posted on:2013-09-20Degree:MasterType:Thesis
Country:ChinaCandidate:Y B LiFull Text:PDF
GTID:2248330374485990Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
Distributed base station was divided into two independent parts, namely, basebandprocessing unit (BBU) and radio remote unit (RRU). CPRI proposal standardized theinterface between BBU and RRU. These made radio product development more flexible,improved products’ compatibility, and ware more conducive to develop the basebandprocessing section and the RF transceiver independently.However, the current repeater connected the radio equipment controller (REC) andthe radio equipment (RE), point-to-point, by CPRI interface. These limited the distanceof the CPRI transmission, increased the costs of building network. In recent years, Thepatent of CPRI transmission based on the Ethernet packet has been put forward. Buthave no Hardware platform to verify its validity and its Ethernet framing is fixed andcan not adapt to the changing CPRI transmission rate and network environment.So, this paper, based on the idea of the CPRI packet transmission, designed andimplemented CPRI packet transmission equipment, which taked advantage of10Gigabit Ethernet packet and flexible framing. The equipment achieved the receive sideclock recovery, the local clock calibration and10Gigabit Ethernet synchronization. Ifthe system code used is different, the equipment can be connected with REC and RE.Firstly, the paper gived a detailed summary of these key technologies, which are usedin the paper, namely,10Gigabit Ethernet, Ethernet synchronization hardwareimplementation, CPRI protocol and other related technologies.Secondly, the paper made the system requirements, which divided into three parts,features, performance and testing, gave the system implementation framework,completed the selection of the system core component and module hardwarecircuitdesign and implementation, completed system schematic drawing by the DxDesignersoftware platform, analyzed the key points of the system PCB design technology,completed the system printed circuit board design used the ExpeditionPCB platform.Finally, according to the system requirements of the functionality testing and theperformance testing, the paper verified the function of the system and performanceindicators by some experiment sample, and made the analysis of test results. In thesynchronous Ethernet mode, the maximum clock jitter is0.0013ppm, the maximumdelay jitter is2.7ns and the maximum BER is less than1012.This design transmited CPRI data packet by10Gigabit Ethernet fiber-optic,improved the data transfer rate and bandwidth utilization. Flexible packet framingimproved the flexibility and adaptability of the design. The design riched CPRI packettransmission design ideas, and used actual case further to proof flexible expansion ofthe CPRI packet transmission.
Keywords/Search Tags:10GE, Synchronous Ethernet, CPRI, PLL
PDF Full Text Request
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