The Study Of FPU Based On FPGA

Floating point operation is widely used in all kinds of engineering and scientific calculation. In the case of higher speed requirement, a special FPU must be used.As the fast development of Field Programmable Gate Array, the application of EDA technology and FPGA design have become hot spots of study. Therefore, this article studies the floating point operation based on FPGA. It mainly studies the floating point expression conforming to the IEEE754standard and operational rules of addition, subtraction, multiplication and division, analyzes the realization method of basic operational functions of addition, subtraction, multiplication and division combined with the existing hardware model of floating point operation and compiles, synthesizes, debugs the program, as well as realizing functional and timing simulation in Quartus Ⅱ environment. The program is written with C language to realize addition, subtraction, multiplication and division of two double precision floating point numbers and transforming the result into binary output of two double precision floating point numbers conforming to IEEE754, in order to verify the simulation result with this result. If the results are the same, the Verilog HDL language program is correct. Because of limited conditions, the program of64bit floating operation can not be directly downloaded to the existing FPGA. Therefore, the floating point addition and subtraction are taken as examples to shorten the floating point number to seven digits and modify the program, and then to carry out simulation, download and configuration.