Research And FPGA Implementation Of Remote Sensing Image Decoder

Along with the improvement of modern image sensor’s spatial resolution and the rapid development of aerospace technology, image compression has become a basic technology. Currently, national space agency obtains images with high quality from space and medical images from high-end medical equipment. The obtained images such as BMP, TIFF or any uncompressed HD images will take a lot of storage space, this brought enormous challenge to the capacity of data storage and transmission bandwidth. In remote sensing, medic and some other special areas requiring high image quality, Sometimes need to lossless or nearly lossless compression to get the high quality of the reconstructed image of image data. Standard JPEG-LS lossless compression can be lossless image compression, or able to achieve error-controlled near lossless data compression.LOCO-I (Low Complexity Lossless Compression for Images) algorithm based on Huffman encoding and the context model are the core of JEPG-LS algorithm. Compared with JEPG2000and JEPG algorithm, this algorithm is characterized with the use of Golomb coding and the injection of error controllable in near-lossless image compression.making it more advantageous in the near-lossless compression and more suitable for hardware implementation of FPGA.But the IP core that the Xilinx company launched for JPEG-LS compression algorithm is expensive,complete packaged and has poor scalability in product development.This article studied the JPEG-LS compression algorithm encoding and decoding principle carefully, and exact analyzed the core algorithm of context modeling, Golomb-Rice coding, run-length and conventional patterns of specific process. In order to verify the hardware realization feasibility, we modeling the encoding and decoding algorithm using C language on a PC and test it with large image data. depend on above all, the system design of the decoder. Taking the real-time decoding into account, using image block decoding method, divides the original image into8blocks then respectively sent them into the8decoding module for parallel decoding.The entire design using the VHDL hardware description language, by functional simulation and static timing analysis, collaborative FPGA hardware development board to verify that this decoder can correctly decode the remote sensing image.The design can meet the technical requirements of remote sensing image decoding compressed.in the aspect of real-time performance and reliability.