Real-time FPGA Application Of Onboard Space Lossless Image Compression Based On LOCO-I Algorithm

As the increase in both resolution and number of bits per pixel of imagining payloads, image volume of satellites became fairly extensive. Satellite payloads mostly operate a store-and-forward mechanism because of the distribution limit of ground stations, whereby the captured images are stored on board and transmitted to ground later on. Affected by restrictions of satellite's volume, weight and power consumption, the ability of date storage and transmission is limited. Mass image date caused tremendous stress to satellite data management. To resolve this problem, real-time onboard image compression technology is an inevitable choice. Most lossy image algorithms can obtain higher compression ratio, but in the expense of much more complex than lossless compression algorithm. Because the images which been obtained by satellites are very precious, sometimes the lossless compression is necessary.The main hardware platforms of real-time image compression are FPGA, ASIC and DSP. FPGA is the best choice among them because of high reliability, low power consumption, high-speed and good adaptability of image compression algorithm. Due to low cost and short development cycle, the FPGA is suitable for small batch system of space missions. LOCO-I(LOw COmplexity LOssless COmpression for Images) is a novel loss compression algorithm for images which combines the simplicity of Golomb coding with the compression potential of context models and make best match of two parts of compression, thus getting high compression ratio in expense of loss complexity. These characters can meet the onboard image compression requirements which are real-time processing and low hardware complexity. This paper focuses on specific applications of onboard image lossless compression and presents the FPGA architectural design based on pipeline and parallel techniques. This design was implemented on a Xilinx XC2V2000.The data throughout is 400Mbps when the clock is 50 Mhz. The experimental results indicate that this design can performed in high-speed, and meet the need of real time onboard image processing.