Design And Verification Of Multiple Exposure Image Block Fusion Based On FPGA

:Any sights seen by eyes and images taken by imaging equipments such as camera are different in real life, in that the nature world contains rich colors due to high dynamic range. In contrast, the dynamic range of the camera is limited. For example, at the time of overexposure, an originally bright scene after imaging will be "white". On the contrary, at the time of underexposure, an originally dark scene in the photograph will be displayed as "black". Hence, a clear image which contains details cannot be obtained directly when imaging. A high quality image can be achieved through multiple exposure image fusion method.Through the analysis and contrast of image fusion algorithms, a relatively simple algorithm for hardware implementation is selected in this thesis. The multiple exposure image block fusion algorithm has been researched in the thesis. The algorithm, based on the idea that images are divided into image block of fixed size, is a multiple exposure image fusion process. At the same time, in the thesis, on the basis of the previous algorithm, considering the restriction of image block fusion on resource conditions, the optimization and innovation mainly on the speed of the algorithm can be achieved by adding a window operator on the algorithm implementation. Thus, it enables the multiple exposure image block fusion to implement fusion operation quickly and completely.Through the study of multiple exposure image block fusion algorithm, a relatively simple scheme for hardware implementation is proposed based upon the MATLAB simulation and C model. In the thesis, based on the idea of modular design, Verilog HDL language is applied to implement separate and joint simulation of algorithm module. The processes of counting pixels, calculating the entropy values, choosing the optimal block, and calculating the weight values have been implemented in the thesis. Besides, the method of weighted fusion is proposed. The functions have been verified fully to prove the validity of the design. The scheme makes full preparations for the final implementation on FPGA of multiple exposure image block fusion algorithm.