| With the advances in semiconductor technology, as well as the SoC technology continues to improve, the integration of transistors on a single chip has reached billions. This means that on a single chip the number of IP cores can reach tens of thousands. In the traditional SoC technology, IP core is based on the shared bus communication, and this pattern has met the bottleneck which had been the case, including aspects like performance, power consumption, delay and reliability. In addition, the emergence of multiprocessor SoC makes bus architecture in scalability, communication efficiency and power problems even more prominent. Facing the problems of bus structure above, people transplanted the idea of computer network communication to the chip design and proposed the concept of NoC (Network on Chip). NoC is based on packet transmission instead of the traditional SoC bus communication, and global asynchronous local synchronous mechanism to complete the high-speed communications between the IP cores. NoC is a larger-scale and higher-level system on a chip, and will be the main direction of future chip design.This paper first introduces the research background and current domestic and international dynamics. Then the NoC-related technical points, including topology structure, switching technology, routing algorithms, flow control, and communication protocols,is elaborated in detail.This paper focuses on the topology structure and routing algorithm and makes some in-depth research and design on the two technical points. First, a new topology structure called generalized hierarchical completely connected networks(GHCC) is proposed, the structure has good characteristics like scalability and uniformity. And it could obtained through simulations that the new structure got a good performance compares to the common-used topology, and even tends to be better. It is a good choice for NoC design. And then, the influence of the input selection for routing efficiency is proved and a new input selection mechanism called block level input selection(BLIS) is proposed. Under heavy load conditions, this mechanism grants the blocking region a higher priority to access the output channel which removes the possible congestion and improves the communication efficiency. No matter which output selection is used, experiments show that the proposed BLIS input selection achieved better performance than the traditional first come first served input selection for most traffic pattern except the transpose traffic pattern, where the two input selection have the similar performance. Even more, BLIS could also enables the low complexity, low hardware cost XY routing algorithm achieve similar or even better performance than the higher complexity, higher hardware requirements OE routing algorithm. |
