Research On Topology And Routing Technology For Hierarchical NoC

Network-on-Chip (NoC) is an important means to solve complex communication problems in Multi-Processor Systems-on-Chip (MPSoC). Current research is mainly for the smaller network. However, as the number of modules in System-on-Chip (SoC) increases, the topology is more likely to suffer from excessive node density and network distance. Taking this in count, more research has begun to be transferred to the point about hierarchical NoC. In this dissertation, a hierarchical NoC study including topologies, routing algorithms and router architecture is discussed.On the basis of the existing hierarchical NoC, a new NoC hierarchical topology is proposed. On this basis, an adaptive source region path selection routing algorithm and a wormhole router architecture based on buffer allocation is also studied. The main work in this paper is outlined as follows:1. A hierarchical region-partitioned CHMesh topology is proposed. As the number of modules in SoC increases, the topology is more likely to suffer from excessive end-to-end hop-counts, causing an increase of power consumption and area overhead. CHMesh is divided into two levels. The bottom level is interconnected with Mesh and divided into several regions, so as to guarantee communications of adjacent nodes, and the upper level employs intermediate nodes to promote the interconnection among different bottom routing regions with CMesh. Furthermore, to increase the upper network communication capabilities, the upper network is interconnected with dual-link architecture. Topological analysis and simulation results show that, CHMesh can effectively reduce the network diameter and the average network distance. Moreover, in the non-uniform traffic patterns, compared with Ref-Mesh, CHMesh with 64 nodes can reduce the average network ETE delay for about 14.9% and enhance the network throughput for about 11.6%.2. An Adaptive Source Region Path Selection (ASRP) routing algorithm is proposed. Due to the concentrated load distribution among the intermediate nodes, the proposed CHMesh suffers from an inevitably local congestion. According to the characteristic of region-partition, this algorithm makes routing decision among the source region instead of source node. Moreover, it distinguishes the adaptive routing node pairs among source-destination node pairs, and enhances the routing selection performance for those node pairs, so as to alleviate the heavy network congestion. Experimental results show that, compared with minimal path algorithm, the proposed algorithm can enhance the saturation injection rate for at most 51% and 34% in synthetic traffic patterns and local traffic patterns respectively.3. A wormhole router architecture based on buffer allocation is proposed. For CHMesh, traditional router design methodology cannot deal with the Head-of-Line (HoL) problems of input buffer in intermediate nodes. Concerning this issue, a new buffer allocation scheme is proposed. With almost no additional area overhead in input buffer, an assistant look-back buffer is partitioned from the original input buffer to temporarily store packets that cannot be routed in a specific period. Furthermore, according to the congestion state in the assistant buffer, it can choose to route or come back to the original buffer, which is a best-effort architecture to ease the heavy HoL problems. Experimental results show that, the use of assistant buffer in input buffer can enhance maximal network throughput for about 9.8% with little overhead.