Design And Implementation Of Dynamic Background Segmentation On FPGA

Automatic image event understanding is the ultimate goal of video surveillance, th background model of visual system is the cornerstone to achieve this goal. Man scholars do a large number of studies on the background modeling and its practica application, promising results and progress have been obtained. This research builds FPGA vision system platform based on practical applications and theoretical studies Researches on classical background modeling algorithms have been investigated an improvement on the previous algorithm has been achieved.This system uses Altera’s DE2-115development board with CyclonelV chip combines the soft core of the device with the soft core of image processing algorithms and integrates Nios Ⅱ processor to execute the improved algorithm. Experiments shov that the visual system can build a good background model, has good performance ii indoor and outdoor testing, and can distinguish moving foreground from dynami background in complex environment. Dual-core system can achieve a rate of3.7/sec a a resolution of320*240with a100MHz processor.The main contents of this article are as follows:1. Analysis of non-parametric and parametric background modeling algorithms Parametric modeling such as Gaussian mixture background modeling and non-parametri modeling such as kernel density estimation modeling have been investigated. Th simplification of kernel density estimation modeling has been achieved through th quantization of pixel values and the online learning of probability density. Unlik traditional KDE background modeling, it does not require to register all the pixel value within an observation duration, and thus reduce the computational complexity and i more applicable for the visual system platform in this article.2. Construction of FPGA dynamic background segmentation visual system. Th system includes a CMOS camera module, FPGA core modules and a VGA displa module. It implements the video capturing, format transformation, zooming, cropping background modeling and image VGA output.3. System optimization and dual-core parallel processing. The system optimization includes the improvement of the algorithm on FPGA and the customization of instructions. The dual-core parallel processing investigates parallel data collection, background modeling and output with dual Nios Ⅱ processor.