Layer - Associate The Photolithography Process Technology Research And Improvement

With the rapid development of the IC manufacture, the key structure of IC is becoming smaller and smaller. Lithography alignment technology is one of the three core technologies, with improved resolution lithography, alignment accuracy requirements are also important. Base on 45 nm technology, alignment accuracy is about 5 nm. This paper aimed to study the overlay in IC manufacture process and get the factor that impact overlay, so that we can improve it.In Lithography process, Overlay is the accuracy of overlap between the current layer and the pre-layer. If the overlay is out of the control limit, the circuit that we design will open or short, and the yield of the product will be very low. There are several type of overlay error, such as translation, wafer rotation, wafer magnification, chip rotation, chip magnification. Overlay is one of the key design rules for the fine pattern alignment machine-scanner, and it’s an important parameter in microlithography. A bad overlay will impact the production yield and quality.There are many factors to the alignment, such as the exposure tool stage moving accuracy, the synchronization between mask stage and wafer stage, the environment of the working condition, the different layer properties induced by different process, the mark signal noise at the wafer.From this paper we will study the factor that impact scanner overlay and improve it by theory analysis and test for lithography scanner. We will study it by three items:firstly, using off axis illumination; Secondly, select the best condition of over mark; thirdly, find the parameter that related the overlay error, and improve overlay by compensate the machine parameter. Introduce the process induced error ("PIE") to improve the layers alignment and overlay eventually.