The Improvement For Device Layer Overlay Precision

Currently, many kinds of electronic product created, such as the cellphone with the better performance, the more convenience Laptop. Amongthese continuously updated products, semiconductor plays a remarkablerole. As the engine of the semiconductor, photolithography contributesmore than other field.Semiconductor product fabricated on a silicon wafer, through theprocess of deposition, photolithography, etch, implant, generating thedevice and the connected wire, eventually forming the product with certainpredefined function. One of the criteria of judging the advance degree of aproduct is the critical dimension defined in the photolithography process.In the current world, the main stream technology is28nm, which is thesmallest critical dimension in the device is28nm.In China, the main streamis65nm for mass production, two generation behind of the world mainstream.There are many layers in the semiconductor chip, these layer will bestacked foll0wing different process, if the current layer is not aligned to theprevious layers with predefined precision, the chip will failed. So to makesure all the layers are aligned is very important in the chip fabrication.Principle the alignment precision is defined as1/3the critical dimension.For the current main stream65nm technology, the alignment precision isaround20nm.There are many factors to the alignment, such as the exposure toolstage moving accuracy, the synchronization between mask stage and waferstage, the environment of the working condition, the different layerproperties induced by different process,the mark signal noise at the wafer. The above factors will be illustrated in the paper and certain solution willbe given, such as using off axis illumination, introduce the process inducederror (“PIE”) to improve the layers alignment and overlay eventually.