The Implementation Of The Portable Asynchronous Loop-back Bit Error Rate Tester

With the development of the data communication technology and network technology, the distributed of data network become more widely. Data communication network has its specific complexity. Each communication link in the network has been connected with a variety of other communication equipments. In the event of failure, it is difficult to distinguish where the failure occurred. Professional staff and special software is needed in order to find out which devices in the chain fail. This resulting in many problems includes repetitive and heavy work which decreases the test efficiency and increase the technical requirement for maintenance personnel. Even worse, it always cannot diagnose the problems correctly. Bit Error Rate Tester (BERT) can be a good help to solve these problems.BERT on the market has fully functional, but in general their size is too large and not convenient, their price are expensive. This thesis describes a portable asynchronous loop-back BERT design based on embedded Linux. Design uses Samsung S3C2440as main controller, use specific error chip DS2172, serial interface chip SP505, E1interface chip LXT360and Cyclonell FPGA logic devices together to complete the BERT function. It’s use Linux command line to display the result and to achieve human-computer interaction.The BERT can complete the general bit-error test, HDLC bit-error test, El bit-error test and specific simulation of business bit-error test. BERT’s maximum testing rate is2Mbps, offers a variety of pseudo-random code and manual code. This thesis introduces the hardware and software of this design in detail, including embedded Linux driver development, logical interface functional design, bit error compare module design, user interface design and the test results management design. Design was verified in the system level, indicating that the BERT can work correctly and meet the transmission system’s requirements in error detection.