Research Of Neuron-MOS And Its Application Circuits

With the development of the integrated circuit (IC) and the improvement of its integration density, many problems have occurred for the conventional silicon IC based on single transistor function. As a functional transistor, neuron-MOS provides us an effective way to settle the problems resulted from the increase of transistor number and the interactive wires. In this paper, based on analysis of the device's characteristics, the accurate SPICE model for this device is presented and the application circuits are thoroughly researched.The characteristics of neuron-MOS are analyzed systemically which provide the theoretic guide for the design of neuron-MOS circuit. The viewpoint that because of the field parasitical capacitance between the floating gate and the bulk the floating gate gain factor v exists a maximum value is presented. The compare of the speed and power loss performances between the neuron-MOS and ordinary CMOS is carried out. The factors that limit the number of neuron-MOS input gates are discussed from the calculation precision, circuit speed and the power voltage.The SPICE model for neuron-MOS is presented which provides a more accurate method to simulate neuron-MOS circuit. When modeling the floating gate potential, the effect of the parasitical field capacitance to the floating gate potential is considered, and the model is verified by the simulation results and the measured results.Parity check system based on neuron-MOS is designed. A 8-bit odd coding circuit and verification circuit are designed and simulated. The results show that neuron-MOS circuits decrease the number of transistors from 500 transistors to 38 transistors.The application of neuron-MOS in digital PWM generator is developed.The number of transistors is decreased dramatically. The output characteristics of the C-neuMOS source follower are analyzed thoroughly, and the threshold of neuron-MOS is optimized between the output voltage offset and the power loss, which provide theoretic guide for the design of neuron-MOS analog circuit.A novel CDMA matched filter structure is presented. Compared to the conventional structure, the number of circuit elements is decreased greatly for the same function. The test chip was fabricated and the measurement result shows that the system structure is feasible and effective. In the design of the matched cell, a novel neuMOS source follower circuit with high precision is presented to eliminate the threshold loss of source follower.