Design Of New DDR SDRAM Memory Architceture(SDDR)

In recent years, serial transmission mode is paid more and more attention and there are already a lot of examples of serial transmission substituting parallel transmission such as USB replacing IEEE1284, SATA replacing PATA, PCI EXPRESS replacing PCI and so forth. Therefore, it is predictable that serial transmission will become the mainstream of data transfer in the near future.The third generation of DDR SDRAM has come into being with higher transmission speed, lower power consumption and wider application. However, as performance increases, it has more and more pins, leading to higher and higher cost. When a great number of pins added to parallel transmission as transfer speed improved, it will cause a rise in cost and signal interference, inflicting DDR SDRAM into the same kind of trouble.In this thesis, a new design of serial DDR SDRAM controller (SDDR) architecture has been put forward on the basis of firstly comparing the development, merits and demerits of different memories. The design idea of SDDR mainly consists of three parts.1.Such information of memory as control command, address, data and so on is packaged and transmitted in the form of message package. And memory is no longer directly accessed through parallel bus.2.Controller of the original memory is divided into two parts. One is connected to the host, which works as the controller of SDDR; the other one, as a part of memory, finishes data parse and so forth.3.Message is transmitted between controller and control interface of SDDR with one-way write-only serial bus OWOSB; information can only be transmitted in one direction, and there are two buses in OWOSB, one is up-link bus, the other is down-link bus.Above all, the design of SDDR controller and control interface is carried out in this study and so is the definition of message frame format in OWOSB. Data conflict is solved through a state bus. Then, simulation verification work is done based on resources available.With reference to a huge amount of materials, schematic diagram of SDDR SDRAM hardware test platform has been designed; routing of circuit board and welding of devices have been completed after selecting chips. And anti-interference ability is improved by adopting filter circuit, magnetic beads isolation and so on. Eventually, design and debugging of six-layer circuit board is achieved and so is the verification work of SDDR architecture.