Research On Modeling And Simulation Of Charge Trapping Memory

For the20nm-node non-volatile memory (NVM) technology. Flash memories with polysilicon floating gate have encountered serious technical challenges confront severe performance limitation:the contradiction between high speed, low power operation and longtime retention. In order to solve this problem, a lot of new non-volatile memory devices have been invented. Among those memories, owing to the discrete storage, the advantages of fast programming/erasing speed, high reliability, process simplicity, low cost, and compatible with conventional CMOS (Complementary Metal Oxide Semiconductor) process make charge trapping memory as one of most attractive candidates to replaces floating gate cell.In this thesis, firstly, a retrospect of the operating principle of non-volatile floating gate semiconductor memories and various challenges to its further scalability is conducted, and then the background and evolution of charge trapping memory is presented. After that, existing problems in charge trapping memory are pointed out and new solutions proposed through analyzing and summarizing the progress.The model and mechanisms of silicon nitride based charge trapping memory is analyzed in detail, including the model of charge tunneling into trapping layer, energetic and spatial distribution of traps, the mobility model and trapping-detrapping process. The trap-assisted tunneling can be ignored because of the high fields in programming and erasing. The energetic distribution range is very limited, although exponential and Gaussian distribution has been proposed, so it can be set to single-energy level. The detrapping process of charge from trapping center is discussed in detail. An electron will not experience the Poole-Frenkel effect if the amphoteric trap model and the hypothesis of all the traps being neutral in fresh device are used simultaneously; a reasonable model is given to resolve the contradiction and applied to the simulation.Above-mentioned models are incorporated in drift-diffusion equation and current continuity equation of charge transport in the storage layer, the coupled equations is discretized using the Newton iterative method in trapping layer, and to solve the equations to simulate the memory programming, erasing and data retention characteristics.Simulations are done with different layers thickness, traps parameters. Increase in tunneling layer result in higher tunneling current and faster programming, but if the overall thickness of tunneling and blocking layer, the programming speed remains constant. Increase in temperature will result in higher tunneling current and degraded retention. Simulation shows that shallow trap level result faster erasing but no influence the programming, this may be caused by higher charge loss for shallow trap level.