Research On SnO₂-based Resistive Random Access Memory And Simulation Of Charge Trapping Memory

The miniaturization of electronic devices are preferred with the rapid development of microelectronics technology.However,the flash memories based on the traditional floating gate structure are facing severe challenges due to the scaling down in feature size,such as the large leakage current,the decreased coupling coefficient between the control gate and the floating gate,etc..There are two major categories to develop new memory devices.The first is the development of the new switching mechanism-based non-volatile memory,such as phase-change random access memory(PCRAM),resistive memory(RRAM),magnetic memory(MRAM),and ferroelectric memory(FeRAM);the other is to develop 3D-NAND charge trapping flash memories to achieve high storage density.Based on this background,we have conducted a study on the new generation non-volatile memory RRAM,a prospective candidate for substituting traditional flash memory,and on the simulation of SONOS structure memory,a basic memory cell of 3D-NAND.First of all,tin oxide is chosen as the active layer of RRAM due to its advantages of wide band gap,low cost,good stability,and non-toxicity.A sol-gel solution with a concentration of 0.1 mol/L was spin-coated on an ITO substrate toobtain a tin oxide resistive layer.After exposed in an ammonia atmosphere and annealed in O2,a 100 nm Al was thermally evaporated as a top electrode to make a typical "sandwiched"Al/SnOx/ITO device structure Then,in order to get better device performance,a series of tentative optimizations were conducted during the process,including spin-coating speed,ammonia treatment,and annealing temperature.I-V measurements were used to study the device switching properties.The results displayed thatthe measuring method had an impact on the device performance.Under certain conditions,the polarity of voltage for electroforming and the value of compliance current will change the device from bipolar to unipolar.Finally,we compared the device's resistance to voltage polarity and found that device characteristics are symmetrical.Finally,the resistive switching mechanism based on conductive filaments was inferred from the linear fitting results of I-V curves on different devices.The formation and rupture of oxygen vacancies conductive filaments render the device switching between high and low resistance state.The I-V fitting results showed that the conducting behavior of Al/SnO2/ITO devices are in good agreement with the SCLC model(Space Charge Limiting Current)model.Next,we use the Silvaco TCAD simulation software to study the SONOS structure memory.First of all,a relatively simple MOS structure was employed to study the influence of dielectric layer thickness,top electrodes,the doping concentration of substrate,the fixed charge in dielectric film,the measuring temperature,and the interface defects on the C-V curves of MOS devices,and is expected to provide a reference for future experimental analysis.Later,we used the DYNASONOS model to construct a standard SONOS model and a structure using a high-k material(Al2O3)as the blocking layer.Through simulation,we visually compared the electric field intensity and energy band of each dielectric layer under the same bias voltage,and the change of net charge with transient time of the two devices.The simulation results show that the high-k material in blocking layer can increase the voltage dropping on the tunneling layer and improve the program and erase performance of the SONOS devise compared to SiO2 intuitively.Then we compared Al2O3 layer with different thicknesses to determine the thickness.The optimal thickness of the Al2O3 blocking layer was determined to be 8 nm according to the writing speed,the reserved net charge,and the retention time.