Research And Analysis Of Digital Down Conversion Based On FPGA

Digtal DownConverter is one of the core technologies of software radio, by widespread application to all kinds of military and civilian radio communication equipment and electronic warfare, radar, and other fields.This thesis introduces the principle of Digtal Down Converter, and discuss therealizable method based on FPGA in detail. DDC is put through A/D conversion of digital series after digital frequency mixing, intermediate frequency signal will move to baseband, and then through the extraction filtering, plastic filter to obtain useful signal process.Because software radio is open and programmable,it require high effcient programmable decimation filters with good anti-aliasing feature which can extract both desired narrow band and wideband signals,it also requires programmable Finite Impulse Response (FIR) filters to reject the out of band signal.FPGA is high-speed configurable logic circuit, its physical and logical layout for the state machine and sequential logic fast implementation and design, single FPGA integrated millions of logic gates, can be used for complex digital signal processing. FPGA programmable, flexible and highly integrated in the software radio has been widely applied. Based on the discussion of the structure of digital down-conversion (DDC) in software radio receiver,this paper suggests the classification of decimation filtering to reduce the taps of the anti-aliasing filters,and the suggestion to use different resources at separate step of decimation filtering during the multiple steps,so as to make the resources of FPGA high-efficient utilization.The module of digital down converter is composed by NCO(Numerically controlled oscillators),CIC(Cascaded integrator comb)filter, CIC Compensator filter,HB(Half-Band)filter and FIR(Finite Impulse Response)fikter.This thesis is based on researching every module,the method of LUT(Look Up Table)must be set for appropriate use of resource in FPGA.For the use of application,parallel transmission in multiple signal channels may be adopted.CIC filter does not require the use of multipliers, only need to use the time delay and the addition operator. In the blocks of efficient filters of DDC,FIR filter plays a key role in rejecting the unwanted signals, Can use window function design, but FPGA based Distributed Algorithm to more efficient implementation of FIR filter, In this thesis right to Distributed Algorithm to carry out in-depth discussion and research.In the design process used by the FPGA Xilinx’s Virtex-5series, the use of the design software Matlab R2010a, ISE10.1, Modelsim6.5.