Design Of 60GHz CMOS Power Amplifier

Advances in multimedia technology make the wireless communication system newrequirements. The current Wireless Local Area Networks (WLAN, such as the 802.11 a/b/g) havealready can’t meet the increasing requirements in transmission rate. For its wide frequency band,anti-jamming capacity, high transmission safety, high transmission data, the 60 GHz technologybecomes the development direction of the next generation of wireless communication system andthe current academia/industry hotspot. Currently, the United States, Europe, Japan and Taiwan’smajor universities and research institutions have conducted 60GHz technology research, andachieved remarkable results.However, compared to the outside’s 60GHz technology research, ourcountry has little research in this area.This paper summarizes the research on 60 GHz CMOS power amplifier, concludes the typicalstructure and design Index. Then, this paper discusses the challenge of CMOS millimeter-wavepower amplifier and design consideration, gives the method of the MOSFET’s sizing. Finally, basedon the IBM 90nm 1P8M RF-CMOS process, this paper designs two 60 GHz power amplifier, andthe main work as follows:(1) Surveying related literatures of 60 GHz CMOS PA (Power Amplifier), typical circuitstructure and technology parameters are given in this article. By the end of 2010, saturated outputpower of 60 GHz COMS PA in IEEE papers increased from 8 dBm on 2006 to nearly 20 dBm.Power gain on 2006 was 5.2 dB and on 2009 was 32.4 dB. Meanwhile, P1dB was raised from 6.4dBm of 2006 to 18.2 dBm of 2010. PAE on 2006 was 7% and changed to 26% on 2010.(2) Aimed to design millimeter wave circuits in CMOS process, research and approach ofdesign method is given. Early time of 60 GHz circuits are realized by compound semiconductorprocess (GaAs or InP), The semiconductor technology advances in CMOS technology makesmillimeter wave integrated circuits possible. However, there are still many challenges in the CMOSmillimeter-wave circuit. The high-loss, low quality factor of passive components is a bottleneck inCMOS millimeter-wave circuit design. The device model supported by foundry does not apply tomillimeter-wave band, making the accuracy of the model is the biggest challenge in circuit design.Meanwhile, the nano-CMOS process makes transistors gate oxide more and more thinning, thesupply voltage and breakdown voltage getting lower and lower, it limits out power ofmillimeter-wave circuit, and should trade-off in circuit design. In addition, the layout is essential tooptimize, which determines the final performance of the chip. Therefore, the millimeter-wavecircuit design requires the methods different from traditional RF circuits. (3)This paper designs tow 60GHz amplifiers using a 90-nm RF-CMOS process with 8metal-layers. One uses Ground coplanar waveguide (G-CPW) to realize accurate values of smallreactance as well as the interconnect lines, the other uses "capacitor unilateralized technology"andtransformer to achieve the signal coupling and impedance matching.With the frequency increases,the parasitic of device and metal connection becomes significant, some of the parasitic ignored inthe traditional RFIC design can no longer be ignored.This 60GHz single-end power amplifierconsiders the parasitic effects, uses the CPW to achieve inter-connection wire and the Bond Pad(parasitic parameters have been simulated) in the circuit simulation. Besides, Transmission lines(T-lines) can be modeled directly due to their inherent scalability in width and length, which is easyto realize accurate values of small reactance by T-lines. This paper uses Ground coplanar waveguide(G-CPW) to realize accurate values of small reactance as well as the interconnect lines. The chipoccupies an area of 1200μm×700μm. The 60GHz differential amplifier uses transformer to achievethe signal coupling and impedance matching. In the second stage, We use a pair of cross capacitorbetween the differential MOSFET, this stage offset the capacitance (CGD) feedback in order toachieve the unilateralized. It can reduce the "Miller effect" and increase stability of common-sourcestructure and the power gain. The chip occupies an area of 711μm×796μm.