Research Of Key Issues And Chips Design For 60GHz Millimeter-wave Receiver Based On Silicon

As the continuous enhancing demands for wireless communication data rate of modern society, giga bits per second transfer rate should be supported in many situations. Since this century, the countries successively release a continuous 5-7 GHz bandwidth around 60 GHz for millimeter-wave short-range high speed transmission applications, such as wireless personal area networks (WPAN) and wireless high definition multimedia (wireless HD). It greatly motivates the researching enthusiasm in both academic and industry for 60 GHz millimeter-wave receiver, and the research fruits come forth endlessly, which are dominated by CMOS technology. As a technology of high integration and low cost, the progress in CMOS leads it sufficient attraction in millimeter-wave band. The study of 60 GHz millimeter-wave receiver based on silicon has a great significance on the popularity of 60 GHz communication technique. Based on the 65nm CMOS technology, the 60 GHz millimeter-wave receiver and the key circuis including low noise amplifier, mixer, intermediate frequency amplifier, low-pass filter and variable gain amplifier are studied in depth in this dissertation.The basic issues of CMOS millimeter-wave circuits design are discussed in this dissertation. The features which differ the millimeter-wave circuits design from gigaherts circuits include the transistors operate close to their extreme frequency, the signal’s short wavelength lead to non-ignorable distributed effects of the interconnect and the parasitic parameters exhibit huge affection on the operating state of the circuits. These features determine the design methodologies and ideas of millimeter-wave circuits. The characters of basic components in CMOS technology include transmission lines, inductors, capacitors and transistors at millimeter-wave band as well as considerations in circuits design are analyzed. The procedure of on-chip passives modeling using electromagnetic simulation software HFSS is introduced, taking two types balun, i.e., transformer balun and Marchand balun for instance, which are modeled and simulated in HFSS, and their properties under resistive or capacitive load conditions are analyzed.The input impedance, transconductance and noise performance of the MOS transistors with all electrodes connected to port impedance are analyzed in this dissertation, and these conclusions can be directly cited in the following circuits design. To achieve sufficient gain, multi-stages in cascade structure are adopted for the millimeter-wave low noise amplifier in this paper, and differential design optimization are performed to different stages according to their features. Common-source topology is adopted in the first stage for better performance of both input impedance matching and noise, while cascode are employed at the subsequent stages to obtain better isolation and higher gain. In order to improve the performances of low noise amplifier in terms of input matching, noise, gain and bandwidth, inductor performance enhancing techniques such as input LC ladders, cascode neutralizing inductors, gate feedback inductors and inter-stage T-shape networks are used in this paper. The low noise amplifier designed possesses a gain of 17.3 dB and bandwidth of 20 GHz, while its noise figure is lower than 5 dB and the modified algorithmic design methodologies for 60 GHz low noise amplifier is concluded. The low noise amplifier structure based on current-reused positive feedback structure is proposed, while its stability, gain and noise performance are analyzed, and the measurement results show it possesses 14.9 dB gain and 16 GHz bandwidth under power dissipation of less than 10 mW, revealing its potential in low power applications.The emerged issues of when conventional Gilbert structure mixer is directly applied to a 60 GHz receiver front-end based on sliding-IF architecture are discussed, especially the relative narrow IF bandwidth of the mixer comparing with channel bandwidth. In order to effectively solve these problems, based on Gilbert cell, the topology equiped with LCR series resonant network and cross-coupled pair is proposed in this dissertation. In this structure, current injection and resonant inductor techniques are adopted at the transconductor stage of the Gilbert cell, as well as paralleled LCR series resonant network and negative conductance introduced by a cross-coupled pair are added at the load stage, to extend bandwidth and compensate the loss of gain simultaneously. By the analysis of the gain and bandwidth, the conclusion of their product increasing as negative conductance strengthens can be drawn. The measurement results show the IF bandwidth is 6.5-17.5 GHz with a 3 dB gain; while its gain reaches 7.5 dB in an IF bandwidth of 8 GHz, demonstrating it possesses moderate gain and broadband characters simultaneously.The receiver applied to a 60 GHz communication system is integrated in this dissertation. The whole receiver link is separated to two chips, and the chip one include low noise amplifier, first down-conversion mixer and IF amplifier, while chip two comprises IQ quadrature mixer, frequency divider by two, low-pass filter and variable gain amplifier. The receiver adopts a dual-conversion architecture based on sliding-IF, where the first local oscillator frequency is 48 GHz, generated by a 24 GHz LO source and a frequency doubler. The IF frequency is located around 12 GHz with the second quadrature LO frequency is obtained by the 24 GHz LO source through a frequency divider by two. All the blocks in the receiver link employ broadband design techniques since the single channel bandwidth in 60 GHz communication systems exceeds 2 GHz, and these techniques are discussed in this paper. The measurement results show these two chips exhibit correct functions while maintain favorable performances, demonstrating the CMOS technology’s brilliant application prospects in 60 GHz communication systems.