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FPGA Implementation And Comparative Study Of Embedded CPU Soft-cores

Posted on:2013-11-03Degree:MasterType:Thesis
Country:ChinaCandidate:M Y MaFull Text:PDF
GTID:2248330362968706Subject:Microelectronics and Solid State Electronics
Abstract/Summary:
Techniques of System-on-a-Chip (SoC) based on Deep Sub-Micron technologyand IP core reuse are the international development trend of the Very-large-scaleintegration(VLSI)and the mainstream of IC techniques in this century. SoC is thecore of embedded system, integrating hardware and software as a unit, on the purposeof the largest inclusion of production system in system integration, and cansuccessfully achieves multi-disciplinary cooperation and integration. More capitalwill be invested and higher trial producing risk will be taken if immediately put intotape out for SoC in some small production or in development stage. Risks can bereduced or avoided if SoC is implemented in large-scale programmable device such asFPGA.Embedded CPU is the heart of the embedded SoC. Embedded processors have alarge variety, so choosing a good processor is an important step for developing SoC.The performance is an important aspect in choosing embedded CPU, and performancemeasurement is an important part in embedded SoC development.32-bit RISCprocessors are widely used in SoC design, such as ARM CPU and MIPS CPU whichare commercial cores, users must pay for expensive licensing fees. Takingconsideration of flexibility, this paper chooses four free embedded processors tocompare performances. They are Nios II, MicroBlaze, LEON3and OpenRISC1200.Performance measurement adopts widely-used Dhrystone2.1benchmark program.The focus and difficulty of this paper are to build hardware system and to modifysoftware program on the purpose of adapting different hardware platform. The role ofa module to improve performance is determined by building smaller systems andadding or removing a module in building hardware system experiments. To modifysoftware program refers to library function in different hardware platform to modifyDhrystone2.1.This paper has done the following work:1. this paper uses Quartus II SOPCBuilder to construct the hardware SOPC system based on Nios II and modifiesbenchmark program in Nios II IDE. Performance data getting from different hardwareconfigurations and software settings can derive modules and settings roles inenhancing performance.2. Xilinx’s Embedded Development Kit (EDK) is used forbuilding a MicroBlaze-based hardware system. Varied with the Nios II experiment onCPU configuration, the CPU has used two different configurations. In softwaredevelopment for Xilinx drivers to modify the benchmark, the generated files will occupy smaller space and run more efficiently.3. GRLIB library is used to configurethe hardware in Linux or Cygwin, and using Xilinx ISE to synthesis, translation,mapping, placing and routing. BCC is used to compile application in software.GRMON is used as scanning the hardware, downloading and running the software.4.using Verilog HDL to construct the hardware system based on OpenRISC1200; usingQuartus II to synthesize this system; using GCC, GDB, Binutils and uClibc toconstruct or32cross-compile tool chains; using Quartus II downloading tools todownload and run software and hardware files.5. Processor system configuration andCPU architecture including instruction set architecture and cache are comparedbetween CPU cores. Easy of Achievability and configuration, area and performanceare the aspects in comparing four CPUs.
Keywords/Search Tags:CPU, Nios II, MicroBlaze, LEON3, OpenRISC1200
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