The Electronic System Level Modeling Of CLB Bus

Along with fast development of the IC design and process, people can integrate a complex electronic system on a small chip (this is so-called SoC). As a part of a SoC, the bus response to some major functions such as information exchange, data transaction and transaciton control etc. of the whole system. So a regularity and function right bus can not only promise the smoothly runing and stability of the system, but also it can promote the performance of the system. And so this leads the design of the SoC bus more and more important. SoC design should be a process that hardware and software are co-designed, but traditonal methodolgy which based on RTL modeling can develop the software only after the finish of the hardware, this reduces the efficiency of the development, delays the time to market and so reduces the competitiveness of the products in market.In this paper, we exhaustively descript the design of the authorized CLB bus based on the ESL platform SoClib which is supported by TIMA lib in France. In this paper we summarize a methodolgy to model the transaction level modeling of the CLB bus, with the object-oriented design techniques use SystemC language to achive the cycle accurate TLM model of the bus of a authorized 32 bits embeded RISC CPU--C*core. In order to enhance its reuseabilty of the CLB IP, we encapsulate our IP with standard VCI protocal, so as to use it in other SoC system.At last, we associate the CLB bus model that we designed with some other models that provided by the SoClib to construct a complete SoC system for our simulation and verification. The test result proves the correctness of our IP model and it also shows that the simulation speed of our TLM CLB bus model is much more faster than the traditonal RTL models, this also promotes the efficiency fo the co-design of hardware and software, at the same time the combined VCI protocol increases the reusability of the CLB bus IP module.