Low Power Design For Wireless Sensor Network Nodes

Wireless sensor network is a kind of self-organized network without infrastructure. It is used for collecting sensor data from the environment. How to reduce the power of the sensor node is very important for prolonging the node’s lifetime.The power consumption of wireless sensor network node chip consists of two parts: dynamic power and leakage power. So our design concerns both of them to reduce the power consumption. To reduce the dynamic power of nodes, we design and implement novel node architecture with low power processor MC8051 and a hardware compression accelerator. We design and test the node chip, and the result shows it reduce the power and energy consumption.When the node is in normal mode, leakage power is very small. But when the node is in sleep mode, the leakage power of memory is a major source. Recently, the application of non-volatile memory is developed fast. And use non-volatile memory in wireless sensor network node is useful because with the non-volatile memory we can cut off the supply voltage and hence the leakage power. At the same time, we use the non-volatile technology in logical cells to make the circuit recover the states instantly after power failures. It can be used in checkpoint processor and energy harvesting circuits to save time and power.The simulation and test results show that this design effectively reduces the wireless sensor network node’s power consumption.