The Research Of Poly-silicon Layout-dependent Stress Model For40nm CMOS

As CMOS VLSI technology progresses to the nanometer regime, several physical effects become significant as a result of aggressive layout scaling. As a result, this causes Vth shift and carrier mobility change, thereby changes the characteristics of the device. In nano-scale circuits, strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties. However, the introduction of these technologies makes the impact of the device layout pattern more significantly.So far, a variety of stress models have been proposed, such as mechanical stress model caused by STI(shallow trench isolation),WPE(Well-Edge Proximity Effect) model,Etch Stop Liner Stress due to Contact Holes, etc. But there is no complete model covering poly silicon layout-dependent effect.This paper reports and demonstrates a poly silicon layout-dependent PSP stress model for40nm MOSFET electronic simulation. The layout-dependent stress model proposed comprehensively takes two kinds of layout effect into account:the space of adjacent poly-silicon and the number of dummy poly. A lot of MOSFET with different layout were drawn and manufactured. In order to accurately simulate the model, the layout parameters and corresponding influence coefficient and model formula are added to the PSP SPICE platform in sub-circuit form. The model redefines two basic parameters of PSP model:μ0and VFBO. To verify this model, layout parameters were extracted by the LVS tool according to extraction rules. Under this model, we use HSPICE to simulate these MOSFETs. From the simulation results, the model in this work fits the test data very well, the Besides, the typical Idlin,Idsat,Vthlin and Vtsat fluctuation as a function of layout effect are also plotted.This paper is funded by the sub-project of the national Ministry of science and technology major projects (core high based)—45nm complete sets of product process and IP-1(2009ZX02023-2-1).