Analysis And Optimum Design Of On-Chip Inductor For RF ICs

The wireless communication revolution has spawned a revival of interest in the design and optimization of radio transceivers. On-chip inductors are important, performance-limiting, large die area components in monolithic radio frequency (RF) circuits, such as voltage-controlled oscillators (VCO), low-noise amplifiers and passive-element filters.Although numerous results of on-chip inductors have been reported, the basic understanding of performance limitations and the procedures for optimizing the quality factor (Q) are insufficient. Most published inductor models rely on numerical techniques, which are not intuitive enough to provide the insight needed in a design process. This dissertation presents physical models that address the electromagnetic phenomena and parasitics important to the behavior of on-chip inductors. Guidelines for the optimum inductor design are proposed from the point of view of the integrated circuits (ICs) design and technology.Inductors have been fabricated in a 0.35μm two-poly four-metal CMOS technology for validating the some proposed techniques and theories without altering technology to improve the Q of the inductor and circuits in this dissertation.Based on the guidelines of the distributed capacitance mode and coupling coefficient formula, the stacked and planar inductors are designed. Using the close die area of the planar inductor with 1.34nH, the stacked inductor realizes 9.9nH inductance. Realizing lnH inductance, the die area of the four-layer-interconnect series inductor only is the quarter of that of the planar spiral inductor. The maximum Q of the inductor that designed by metal 3//metal 4 in series with metal 1//metal 2 is 110% greater than that of the planar inductor with same inductance.The electromagnetic theory indicates that the metal with small cross-area has the weak skin effect and the inductors with the less ratio the turn width of the space between turns have weak proximity effect. Thus, the one turn metal of the inductor is divided into multi-shunt tracks with the same impedance, and then the maximum Q has 40% improvement.Dual pn junctions in lateral and vertical directions are formed by diffusing the p~+ on the patterned n-well in standard CMOS technology, which are inserted under the inductor. The p~+-diffusion layer is grounded to shield the substrate from the electric field of inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n-wells, and then quality factor is improved by 19%. This phenomenon validates the physical models of the electric field and magnetic field losses of the on-chip inductors in the substrate.