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Dbf Weight Processing Circuit Design And Realization

Posted on:2013-02-02Degree:MasterType:Thesis
Country:ChinaCandidate:Y HeFull Text:PDF
GTID:2218330371960182Subject:Circuits and Systems
Abstract/Summary:
The active phased array radar with digital beam forming (DBF) technique has many excellent advantages, such as adaptive interference suppression and simultaneous mult-beam forming and so on. So it is always a hot research topic in radar array signal processing field. Nowadays, the DBF technique has been developed from the stage of concept and key technique breakthroughs to the actual system application. It is an inevitable choice for next generation high-performance radar systems.In this paper, under the support of the DBF receiver array program, a digital beamforming implementation scheme is proposed based on FPGA and PowerPC's according to demand of the DBF processor with widely data interface bandwidth and high processing ability. Then, the realization of multiple-beam forming for the DBF processor is researched. Xilinx Virtex5 series FPGA-XC5VSX240T is used as the algorithm realization platform. The 2.5Gps×8 high-speed bidirectional optical fiber interfaces and the data-stream drivened weight processings of DBF muti-beam forming fuctions are all completed in this paper, followed with the function realization of the baseband data and the DBF weight coefficients interaction between FPGA and PowerPC with the lOGbps-bandwidth S-RapidIO. Finally, the testing platform of DBF processor is constructed and the performance of the DBF processor is measured, which verify the correctness and effectiveness of the muti-beam forming realization above.
Keywords/Search Tags:digital beam forming(DBF), DBF processor, high-speed serial interface, FPGA
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