Design And Research Of FPGA Based On Antifuse Technology

Field-Programmable Gate Array (FPGA) is programmed by the user to achieve varieties of functions which contain configurable logic blocks and routing resources. Digital system designed with FPGA is flexible, low-cost, low-risk and has short development cycle. Antifuse-based FPGA makes the device to achieve the appropriate logic functions by burning its internal antifuse arrays one time, and it has widely applied in high reliability, high-security military and aerospace fields with advantages of low power consumption, strong anti-interference and anti-radiation. This paper analyses all kinds of researches in antifuse FPGA at home and abroad, discuss the structure of the antifuse FPGA devices and focuses on the approach of antifuse addressing and programming. Early schemes require the use of an individual control line for each routing track, but with the increasing integration, it cannot meet the design requirements. Therefore, it is crucial to improve the layout of the arrays. The impedance in branches of traditional addressing and programming approaches makes the smaller programming current flowing through the antifuse and higher programmed antifuse resistance, limits the driving ability of connection and velocity of propagation. In addition, the voltage of the other antifuse in the same vertical channel on the other end is uncertain, so the antifuse is easy to be programmed falsely. To solve the puzzle, we propose a new method of addressing and programming, it enhances the antifuse programming reliability by increasing programming branches and pre-charge before programming.First, this paper outlined the characteristics of FPGA, and compared with the ASIC, CPLD, analyzed the difference between the three types of FPGA, determined the antifuse-based FPGA for the study. Second, we built the overall architecture of the FPGA, researched the programming routing resources and addressing programming circuit for FPGA devices in this paper, got the length of each routing resources and connections, and ports configuration situation in different modes. Third, based on the tradition of antifuse programmable logic array structure, we focused on addressing and programming of the antifuse FPGA, to make up for the deficiency of traditional programming methods. Finally, a FPGA circuit has been designed and has given the corresponding testing scheme, as a core military project of CETC58 institute, now this chip has been fabricated under the 1.0μm 2P2M ONO process. The circuit has 1200 Programmable Gates, and uses CPGA84 package, its maximum operating frequency is up to 75MHz. Test results showed that the new addressing and programming method was feasible.