Research And Implementation Of Reconfigurable Macro-pipeline Accelerator

People nowadays require higher and higher computation performance in the scientific researches and the technical applications. The traditional processor can hardly deal with numerous complex data. The accelerators are needed to assist the calculations.The accelerators hire spatial parallelism to speed up the computation with multiple process elements but lack in the scalability and the flexibility. More and more researches aim to imporve the scalability and the flexibility. The reconfigurable accelerator and the scalable architecture have become research hotspots.This research designed and implemented the reconfigurable macro-pipelined accelerator. Combined the spatial parallelism and the temporal parallelism, the system accelerated multiple kinds of DSP algorithms with the high performance and the scalability. The research also used the theoretical derivations and the experiment results to verify the scalability.The innovations are: this dissertation presents a novel macro-pipelined systolic accelerator architecture; the bandwidths are reduced by data reuse; the accelerator can be reconfigured to process multiple applications. Implemented on the Virtex-6 XC6VLX240T FPGA, the proposed accelerator operates stably at 200MHz and achieves a peak performance of 51.2 GFLOPS. The dissertation is also significant in presenting a new accelerator system.