Some Reconfigurable Design And Implementation Of The Aes Algorithm

Reconfigurable computing system has been developed based on microprocessor and ASICs. It can achieve potentially much higher performance than software, while maintains a higher level of flexibility than hardware. Many applications have shown to exhibit significant speed-ups using reconfigurable hardware, including: data encryption, signal processing and pattern recognition. Partial reconfiguration is a rising technology. When one module is being configured, others can still do their own job. It can realize time sharing of system resource. Compared with early reconfigurable computing technology, partial reconfiguration improves resource utilization and system's performance.At present, most of the domestic research in reconfiguration is based on FPGA. Successful applications are still on the level of static reconfiguration. Dynamically reconfiguration is still on research, and faces the bottle-neck of reconfigurable interval. When being reconfigurated, chip's IOs take on highZ state. And it can only resume its logical function when reconfiguration is done. This time interval is called reconfigurable interval.Aimed at above question, this dissertation has proposed a design mothod of partially reconfigurable AES arithmetic. And have a deep research on this mothod based on module, mainly include: Firstly, the research status and research significance of reconfigurable computing are introduced, and the existing problems are analysed. After understanding the AES theory, the partial reconfigurable AES based on module is proposed, and the verification scheme is also proposed.Secondly, the design flow of partial reconfiguration based on module is dissertated in detail in this dissertation; aes code based on partially reconfiguration is designed; constraints of reconfiguration are designed. Some problems in the process of realization are analyzed and resolved. Then this partially reconfigurable system is realized on Xilinx Virtex-II Pro FPGA. The predominance of this design method is proved through experiment result.Lastly pipelined reconfiguration is analyzed, and A pipeline reconfigurable system is proposed. This system can realize overlap of reconfiguration and task execution, and has an effect of hide of reconfiguration time. It was simply tested by AES, and this does a prophase job for later research work.