Full-function Phase Change Memory Chip Design And CMOS Post-processing Integration

Phase change memory is one of the most promising candidates of the next-generation nonvolatile memory considering its high speed, low power consumption, high density, anti-fatigue properties, compatibility with the CMOS process, anti-radiation, and other characteristics. This thesis describes the design and fabrication of a full-functional phase change memory chip.This dissertation introduces the overall design of the chip, selecting elements of the memory array and the working principle of circuit modules including writing circuit, reading circuit and logic controller. The optimized writing and reading circuit is regulable. The SMIC 0.35 micrometer and 0.18 micrometer process is adopted to implement this design. The amplitude of the generated RESET pulse is from 0 to 4mA; and that of the SET pulse is from 0 to 2mA. Reading circuit could translate the information stored in the cells'resistance to logic output 0 and 1. The reading access time is 9 ns.Then the thesis designs the structure, material and processing method of the phase change memory cell, and successfully integrates the CMOS circuit die and phase change memory array. The passage describes an asymmetric T shape cell structure whose top electrode and bottom electrode is tangential in horizontal direction, adopt Ge2Sb2Te5 and superlattice like material as phase change material, and use lift-off technology to fabricate the cell. In the CMOS post-processing, the passage introduces the co-design of circuit layout and masks of the cell array, and shows the microphotograph of every layers of the cell. The state of the cell could change between crystallization and amorphous state repeatedly. The RESET time is shorter than 5ns. A full-function phase change memory chip has been successfully fabricated.