The Design Of SDIO HOST Controller

With the development of information technology, SDIO (Secure Digital Inputand Output) has been widely used in various SoC project, and become one of theimportant interfaces of a portable electronic device. This design based on the national"863" project, "Reconfigurable Multimedia SoC chip" design, has completed thedesign of SDIO Host Controller IP based on AHB bus.After analyzed and study the SDIO host controller protocols, this paper designsthe the SDIO host controller's framework. According to its internal data flow pathAccording to the transmission characteristics of its command flow and data flow , theSDIO host controller is divided into five parts, ,AHB bus interface Unite , bus controlunite , synchronization module , FIFO interface module card from the machinecontrol unite . In order to improve the performance of the SoC system , this designsupports three mode of DMA controller , which are SDMA , ADMA1 and ADMA2and a query mechanism of interrupt .In a low power project , the designer can set the transfer mode of DMA, thedepth and the transfer mode of the internal FIFO and the external RAM connectionsof this SDIO host controller in the low-power mode , through configuring someparameters . This design uses the finite state machine decomposition technique ,which can reduce the costs of the design in the power and area .This paper designstwo global state detection mechanism for the bi-derection dual port synchronousFIFO , one of them is one cycle set bi-derection dual port synchronous FIFO , whichcan transfer the empty/full state to the read /write controller in one cycle , when theFIFO is in the state empty/full state , and block operate bi-derection dual portsynchronous FIFO , which is used in the mode base on the block operate ,which hasthe advantage of high efficiency of bus .This paper conducted the design and implementation, validation, logic synthesisand time-series validation optimization of the SDIO host controller. Based on theTSMC65LPCMOS CMOS standard unit library process . SDIO host controllerrealizes the external biggest 200MHz clock frequency, area is 61003.910599um2,power consumption for 39.3669uW. It carries out logic validation and FPGA designvalidation. Result shows that the design of SDIO host controller functions correctly,has met the performance requirements of the project. The SDIO Host Controller IPcore has been used in Reconfigurable Multimedia SoC chip.