The Design Of The SDIO Interface Of An Embedded 32-bit MCU

A great progress has been made in the design of MCU, especially embedded MPU, thanks to its low power consumption, and high performance. The research and development of RISC CPU, as embedded system, is vital for the development of SOC (System On a Chip).This subject has completed the whole design of the SDIO extended interface of the 32-bit RISC MPU based on the MIPSX5 instruction system, from RTL level hardware description, functional simulation to FPGA verification. In addition to meet the standard agreement, through a special internal state machine design, the design of the SDIO interface can support the maximum clock frequency range has been significantly expanded.Used of positive (TOP-DOWN) chip-design process and Verilog HDL language, the design of the SDIO interface completes Register Transfer Level (RTL). Firstly, the specification of SDIO controller is introduced, which includes the command and data format, important SD-bus actions, important commands and response and the construction of SD/MMC card. The hardware design of SDIO host controller is proposed, which could be partitioned into two parts: Memory Management Unit and data-command transceiver controller (SDI_TOP), the detail information is described in this article. Software architecture, including command and data transfer and FAT16 file system, is also introduced.Functional simulations based on simulation environment are used to evaluate SDIO host controller performance and parameter. To guarantee the correctness of the SDIO host controller, FPGA verification system is used to verify it.FPGA verification demonstrates that function of SDIO host controller is compatible with SDIO spec 2.0. The speed of read-transmission between host controller and SD memory card is 8193.16Kbyte/s and that of write-transmission is 7496.02Kbyte/s.