A M5 Based Simulation Of Hybrid Memory System And Its Application

Phase-Change-Memory (PCM) has emerged as a promising alternative of DRAMinlargescalemainmemorysystem. Anewhybridmemoryarchitecture, whereDRAMserves as cache of PCM main memory, has been proposed to leverage PCM's highscalability and DRAM's fast access time.One of the biggest issues of PCM is the limited number of writes to its storagecells. The current research mainly focus on uniformly distribute write request (wear-leveling). However, in this paper, we argue that good cache mechanism will decreasethe write times of PCM dramatically in such hybrid memory architecture, while thewear-leveling techniques are still applicable. Nevertheless, the cache in hybrid mem-orysystemarepronetomaliciousattacks. MaliciousprogramsmayforceDRAMcacheto generate large sequence of write-backs to certain PCM cells, which lead to the wearout of PCM device. In this paper, we describe an attack, which exploits the set asso-ciative feature of cache, that repeatedly writes to several addresses which are locatedin a single set and force the set to write-back constantly. To resist the attack, a novelapproach called Randomized Address Remapping (RAR) is proposed in this paper tohide the mapping details between DRAM and PCM, as well as distribute the attackingaddresses to di?erent sets. With this approach, the write-backs caused by the attackcould be reduced dramatically. In addition, this paper proposes Static RandomizedAddress Remapping (SRAR) and Dynamic Randomized Address Remapping (DRAR)according to di?erent cases.As PCM and hybrid memory system is not widely manufactured, to validate andverify the correctness of such approaches, system simulation is always helpful. M5 isa open source, modular, and famous full system simulator, and is widely used among researchers. We modi?edM5 to implement both hybrid memory systemand RAR, andrun SPEC CINT2006 benchmarks together with malicious program on the simulatedsystem architecture. Experimental results show that RAR approaches have reduced nolarger than 0.15% of cache hit rate for SPEC benchmarks, and they have increased nolarger than 1% of cache write miss rate. Moreover, RAR approaches could resist themalicious attack we proposed e?ectively. When the cache satis?es certain condition,they could even reduce the cache write miss rate cause by the attacking program downto 0.