Adaptive Dynamic Address Remapping In PCM-based Hybrid Memory System

Phase-Change-Memory (PCM) has emerged as a promising alternative of DRAM in high capacity main memory system because of its great scalability. But it can only endure a limited number of write. There have been some researches focusing on solve this problem, including wear-leveling method that distributes writes on PCM evenly, and write-reducing method that reduces write number on PCM. A study has proposed a new hybrid memory architecture in which PCM is the main memory, and DRAM serves as PCM`s cache. It can exploit both the fast access speed of DRAM and capacity advantage of PCM, may be a good choice for future memory architecture. A DRAM cache only with high utilization and hit rate can reduce the frequency of write-back on PCM. If a malicious program can create a continuous write-back from DRAM to PCM in some way, PCM`s life will be rapidly consumed. This article shows an attack program which is deliberately designed on tranditional set-associative archetecture.For this problem we propose a static random address remapping (SRAR) method. It adds an intermediate address between PCM`s physical address and DRAM cache. Relationship between Intermediate address and DRAM cache follows set-associative, while physical address to intermediate address will perform a random remapping when the system is powered on, to hide the relationship between PCM and DRAM and prevent attacks based on set-associative.In a system with SRAR, when OS is compromised, the relationship between PCM and DRAM is still likely to be inferred. Therefore, we propose dynamic random address remapping (DRAR) method, which will dynamically change the remapping online when needed. In order to reduce the number of additional PCM writes caused by remapping change, DRAR divides PCM address space into regions, DRAM cache address space is divided into the same number of areas. One DRAM region and one PCM region constitutes a separate set-associative structure. Each region owns a counter to record the number of write-back from DRAM in this region. When the counter reaches or exceeds the threshold value, we think there may be a malicious attack, and the remapping must be re-constructed in this region.There is a problem in the judging standard using write-back times, that is, a normal program will still create write-backs on PCM, when the write-back number reaches the threshold, remapping will be re-constructed, which is not necessory . So we further proposed adaptive dynamic address remapping (ADRAR) based DRAR. We analyzed and pointed out that in a system under attack, write-back rate will remain rather high within a long period. Depending on the "period" basis, we proposed a process-based attack detection and memory-based attack detection. In the process-based attack detection method, we take an operating system time slice as the "period" basis to count the write-back rate, and determine the appropriate threshold value between 20% and 100%. Meanwhile, the memory-based attack detection method takes fixed memory access times as the "period" basis. We made some experiments to record times of situations that attack state is taken mistake as normal state, or normal state is taken mistake as attack state, under different period lengths and write-back rate thresholds. From the result we conclude out a best period length and write-back rate threshold.