Memory Integrality Verify Oriented Cache Design

Today, computer viruses are no longer just threats to X86-based platform, but rather gradually into the embedded systems, and anti-virus software as Rising installed on mobile phones is nothing new. However, the development of the virus in one day, while the corresponding anti-virus technology do not make any break through. Today's mobile phone virus is now emerging, but the anti-virus software to prevent 2 significant limitations: lag and taking the limited CPU resources. So now virus protection, hardware-based architecture is concerned by the world. This article will design the memory integrity verification mechanism which base on this concept.This article first discusses the principles of memory integrity verification, and preliminary design. Cache and AES-GCM is the core of the program's two major parts, and this is one of the work accomplished Cache design. Then researched the principle of the Cache, structure and parameters, and focuses on the various parameters on Cache Performance. This article is divided into two parts Cache were designed: the main part and interface part. Reason for this design is only part of the interface to modify the Cache IP can be transplanted to any system platform. For the main part of the design focuses on the parameter selection, the state machine design and PLRU replacement algorithm. Focused on the interface part of IPIC's 3 bus standard transfer mode protocol and timing. Merge the 2 Parts of the Cache and complete the functional simulation. Finally, the Cache for the IP core developed into EDK project completion of a consolidated and FPGA, and system platforms in a real validation of their logic is correct or not. Verification results show that the completed design to the intended objectives.The main task is to not stop at Cache of the functional simulation, but also to develop a complete IP core,,can be added to the actual PowerPC platforms.