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An Efficient Cache System For Hybrid Memory

Posted on:2017-06-01Degree:MasterType:Thesis
Country:ChinaCandidate:Y C JiaFull Text:PDF
GTID:2348330503489873Subject:Computer system architecture
Abstract/Summary:PDF Full Text Request
With the development of in-memory computing, scalable and energy-efficient memory architecture has been the key factor of development of further development. However, current DRAM-based memory system cannot meet these requirements. Emerging NVM brings new opportunities to resolve the problems of current memory system, because NVM has the advantages of non-volatility, scalability, and power efficiency, etc. However, completely replacing DRAM with NVM still exists some challenges, since NVM usually suffers from limited write endurance and slow write speed, etc. Hence, special attention should be paid to the above write obstacles, because they are the bottleneck of NVM technology.Under the hybrid memory architecture with DRAM Cache and NVM Memory, reducing writebacks from cache to NVM memory is effective to the write endurance of NVM. The locality of victims from cache, which is discovered by the our experiments, can be used to direct the page replacement of our proposed cache policy VAIL(Victim-Aware Cache Policy for Improving Lifetime of Hybrid Memory) for simultaneously keeping the access hit ratio and reducing wirtebacks to NVM memory. Meanwhile, VAIL takes the access characteristic of cache page into consideration to further reduce writebacks. In addition, the pages that have never been evited from cache recently also have greate impact on the performance of cache. So, the adaptive space allocation mechanism is proposed in VAIL to adjust the space of two kind of pages in cache and adapt to the varied patterns of access requests, which is friendly to the cache performance.Our evaluations with different kinds of workloads show that the proposed technique could effectively reduce writebacks for lifetime of NVM and keep the access hit ratio for performance of cache. More specifically, compared with the traditional LRU policy, VAIL can achieve 17% and 22% lifetime improvement respectively in single-core and multi-core system. Meanwhile, the overheads introduced by our cache policy are negligible.
Keywords/Search Tags:Non-Volatile Memory, Cache, Locality, Write Endurance
PDF Full Text Request
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