Design Of 1.8V Low Power 8KS/S 12-Bit R-C Successive Approximation ADC

As described by Moore`s law,over the years,integrated circuit technology are getting smaller,more high precision,more matching and lower supply voltage.For digital circuits is no doubt good.For analog circuit,though the lower supply voltage cause certain restriction,but the more high precision and matching impove the accuracy.Such as the SAR ADC present in this paper,general SAR ADC is usually 8-10bit,but this years,because of the technology develop,making the 12-bit SAR ADC implementation as possible.The 12-bit SAR ADC presented in this paper,its frequency is 125KHz,input signal range is 0-1.8V,power supply voltage is 1.8V,power consumption is 0.54mW.The main structure,include SAR ADC comparator,sample-hold buffer amplifier,bias circuit,DAC and digital control circuit.DAC is grouped by voltage and charge scaling DAC,and is combined with the comparator offset cancellation circuit,which cut the number of capacitor. In the circuits of sample and hold, sample and hold buffer is used to decreased the input resistance, and time of charging the capacitor is diminished by the sample and hold buffer. Input offset storage technic to correct the offset error. PTAT circuit is pushed in bias circuit, bringing a bias current of 5 mA which is direct proportion to temperature. Digital control circuit is implemated in verilog hardware describe language.After the design of circuits,the layout of the circuits is designed. The SAR ADC is used in IP, so there are no ESD protection and PAD.And then the postlayout simulation is done,the results is satisfied the target proposed.