Research On Lossless Compression Technique Based On FPGA

In some special dynamic testing system, lots of test points and higher sampling frequency will produce large amounts of data, which brings some challenges to wireless transmission and storage. The most direct and effective way to solve the problem is to compress the test data losslessly. Research on hardware realization of data compression technology has important significance for improving real-time data transmission.The theoretical analysis and application of lossless data compression are studied in this thesis. The related basic theory of data compression is introduced, the information entropy of test data is calculated by using Shannon information theory formula, the characteristics of several existing lossless algorithm are summarized. According to the characteristics of test data, the LZW algorithm is selected based on the analysis and comparison of combinational compression and LZW compression, which is simple logically and is easily implemented in hardware. Then the software modeling is established to verify the correctness of algorithm by using C procedures, which lays the foundation for the hardware implementation.The system design scheme is presented based on FPGA, which uses LZW algorithm to compress test data in real-time lossless system. The core device is Altera Corporation's EP3C16F484C6 chip, the structure of the hardware compression system is put forward. Using modular design method, the whole design adopts synchronous time design to realize each functional module. The dictionary is structured by applying FPGA on-chip memory resources; also the design takes full advantage of parallel features of hardware description language to layout a new parallel structure and improves data handling capacity.After the design is completed, the test code is written in Modelsim environment to conduct functional simulation for the whole design, and the results indicate that the data can be compressed correctly. Quartus II software is used to synthesize project and analyze timing, resource occupancy and timing requirements are met, the maximum operating frequency is up to 57MHz. Finally, functional testing and performance analysis are carried out for the hardware compression system, the maximum compression speed reaches to 14MByte/s. Compared with software compression, and hardware compression has a great advantage in speed. A great many of experiments reveal that the system is stable and reliable; also the compression effect is obvious for some experimental data.For example, oil pressure and shockwave test data have compression ratio R of 25% to 35%, chamber pressure test data has compression ratio R of 10% to 16%. The design objective is achieved.The hardware compression system has been applied in oil downhole pressure test system.