Design And Implementation Of Double-precision 64-bit Floating-point Division Operation Unit

Floating-point can expresses high-precision and very large value,meanwhile graphics acceleration and digital signal in scientific researchand engineering applications, the demand of floating process is becomingmore and more exigent, floating point unit has become an importantcomponent in modem microprocessor. There is still big optimizationspace for floating-point division due to the special nature and thedifficulty to achieve. As a infrequent operation in floating pointcomputation, a tiny improvement to division may result in big changes tothe whole performance of the processor. Therefore, design a floatingpoint division computation structure, whose implementation is moreefficient, can make great improvement to the performance of processor.NisoⅡprocessor is a RISC cpu which bases on Harvard architectureand uses pipelined technology, it is optimized to Altera's programmablelogic chip and the thinking of system on programmable chip. As aconfigurable general-purpose RISC processor, it can be built as a SOCsystem which is combined with user-defined logic, and the whole systemcan be downloaded to Altera's programmable device. FPU servicesCPU, so if we combine the floating point division unit with NiosⅡsoftprocessor, it would be appropriate for validating correctness of the unitand also has good utility.In this paper, the theory of various currentdivision algorithm including Newton Rapheson, Goldsehmidt, restoringdigit recurrence, non-restoring digit recurrence and SRT algorithm areanalysed, the speed and efficiency of these algorithm is evaluated. Andthe basic theory and key characteristics of SRT algorithm are focused;Aiming to IEEE-754 floating point standard, a design of double precisionfloating point division which is based SRT-4 algorithm is presented. Theoperation unit is completed by using VHDL hardware descriptionlanguage, and it is combined with NiosⅡprocessor through Avalonswitch fabric by using SOPC Builder, and the whole system isimplemented based on Cyclone FPGA hardware platform. Meanwhile,the operation unit passes black-box test and white-box test, it proves that the scheme is correctly designed, and have a faster speed, thus possessgood practical.