Research On Mutation Testing In Functional Verification Of Digital Integrated Circuits

With the rapid increase of the scale of integrated circuit designs, design verification is becoming more and more important. Since simulation is highly scalable, it is still the main method for functional verification. Unfortunately, due to the growing complexity of designs, the partial verification in simulation is becoming an increasingly outstanding problem. Therefore, it is important to propose more accurate and more meaningful quantitative evaluation methods to improve the efficiency of simulation.In the field of simulation quality evaluation, current researches focus on coverage evaluation. There are two aspects of coverage evaluation:on the one hand it can be an inspiration scale to evaluate the completeness of simulation; on the other hand to guide the testing generation based on uncovered part. The common methods which used in industry are code coverage, condition coverage, toggle coverage and path coverage, etc. However, these methods can't fully meet the needs of design verification since they are too simple or too costly to compute.Mutation testing is a fault-based approach for software testing. The basic idea behind fault-based approaches is to show that particular faults cannot exist in the software by designing fault specific tests. In mutation testing, faults are introduced into the original program by creating many faulty versions of the program. Each of them contains one fault. The faulty programs are called mutants of the original program. Mutation analysis requires executing many mutants to kill them. The rate of killed mutants used to evaluate the quality of the test data, and the un-killed mutants can guide testing generation.In this paper, we combine mutation testing and functional verification together, studying the application of mutation testing used in evaluating the quality of functional verification. First of all, based on software mutation testing, a new hardware mutation testing approach is proposed to evaluate digital integrated circuit functional verification. This approach applies to such a kind of circuit described in Verilog HDL. Then, according to the aforementioned method and the Verilog Procedural Interface, we also implement a hardware mutation testing prototype tool based on Linux operating system. Finally, some experiments are carried to validate the effectiveness of the hardware mutation testing system used in evaluate functional verification quality.