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Based On Nios Network In Real-time Encryption / Decryption System Design And Implementation

Posted on:2012-12-04Degree:MasterType:Thesis
Country:ChinaCandidate:J DingFull Text:PDF
GTID:2218330338955872Subject:Computer software and theory
Abstract/Summary:PDF Full Text Request
This paper discusses and designs a real-time encryption system about network data transmission. Because the transmission data is so large and the safety is very low to the current network, so the data on channel is transferred in cipher text.First of all, this paper uses the advanced encryption standard which is popular in domestic and international at present as the encryption algorithm in this system. Then according to the characteristics of the algorithm, it is realized by the hardware description language and optimized, to meet the processing speed of the real-time network. In order to make the encryption module flexibly used in Nios II as a customized component, this system designs the corresponding interface and its address space mapping by Avalon bus interface specifications. In this paper, the Nios II processor, the customized AES-256 encryption component, the network controller and the corresponding peripherals such as memory are integrated into an encryption hardware platform by SOPC technology. And programming the corresponding software realizes automation control, making it become a real-time network encryption system.The encryption module uses reconfigurable technology in designing S-box could be configured a better performance at any time. It uses on-chip memory and the management to key and original data is adopted the dedicated storage, realizing locking technology on the key and original data. Once the input, users can't read from the bus again, to avoid the possible stealing the information from memory, increased the system security, making the whole design with a higher safety, reliability and flexibility. And the structure uses on-chip memory as the data buffer pool to handle the speed gap between the network transmission and hardware processing, so as to speed up the processing speed.At last, the system is synthesized and wired by the QuartusⅡ8.0 and downloaded to the Altera EP2C20F484C6 chip. The timing simulation can normally work in the 91.98 MHz clock frequency. It can completely meet the real-time encryption speed of the network transmission in daily life. So this embedded system can be widely used in the field of information security.
Keywords/Search Tags:data encryption, Avalon bus, SOPC, NiosⅡ
PDF Full Text Request
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