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Research On Channel Coding For Digital Video Broadcasting Based On FPGA

Posted on:2012-08-11Degree:MasterType:Thesis
Country:ChinaCandidate:Z L HouFull Text:PDF
GTID:2218330338955120Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
In recent years,the use of cable distribution for the delivery of video and audio signals to individual viewers and listeners has entered innumerable families, and has already become the dominant form of distribution in many parts of the world. Meanwhile, the video quality and quantity of programs of people's demand is increasing every day and night. And, the transmission quality and efficiency of digital TV signal effects the television industry development,but channel coding quality directly influence transmission quality and efficiency. Therefore, the research of digital television channel transmission has a special meaning.The specification of channel coding in our country is according to the European standard ITU-T J.83 formulated, so in our QAM modulators, channel coding part is mostly used the ASIC chip which foreign manufacturers support ITU-T J.83 Annex A .Such ones generally provide only 2 or 4 channel ASI input, its design flexibility limited is obvious. Meanwhile, in the cost and the resource are also restrained. The FPGA technology made the design flexible and reduced the costs and development cycle. Using the FPGA we design and implement the DVB– C channel encoder, and in FPGA chip we solved many problems such as multi-ASI inputs, design flexibility and the costs.The study in this paper mainly based on the SARFT released GY/T 170-2001 standard and FPGA technology. We select the Cyclone III family FPGA EP3C25Q240C8N as the main chip, using the Verilog Hardware Description Language, and implement the channel encoder in DVB-C system. The FPGA design part adopts the top-bottom design method, DVB - C channel coding system is divided into four modules: Sync 1 inversion and randomization, Reed-Solomon (RS) coder, Convolutional interleaver and Byte to m-tuple conversion module. In this design, synthesized using Quartus II software, verified using Modelsim software and SignalTap II software. After verification, the function and timing of the channel encoder meet the standard of DVB-C system. Finally, we design the hardware circuit using Altium Designer software. Further proves the practicality of the channel encoder in this paper.
Keywords/Search Tags:DVB-C, Channel Coding, FPGA, Digital TV
PDF Full Text Request
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