FPGA Dedign And Study Of The FCB In DMB-TH System

Digital technology has being the main driving force of extending the Radio TV services and promoting the Radio TV industrial upgrading of the world. And, people not only can receive the TV signal from the cable, but also from the satellite, the ground or the mobile communication network with the digital technology.Digital TV signal will produce distortion and error, because of the influence of a variety of channel noise and multi path fading, or other interference factor, during transmission. Therefore, in order to ensure the quality of the digital TV signal and the system reliability, people often adopt channel coding techniques in the digital TV signal transmission system. Now, it has three digital terrestrial TV standards that have come into the practical stage, namely: DVB-T in Europe, ATSC in the United States and ISDB-T in Japan. In August 30, 2006, the Standardization Management Committee of China announced formally digital terrestrial TV and broadcasting standard with independent intellectual property rights. The goal of the DMB-TH system standard is to build multimedia wireless transmission network that can provide mobile TV services.In first chapter, this paper introduces the domestic and international current development of the digital Terrestrial TV, and the development of FEC. In the second chapter, it discusses the system structure of the transmitter, the system technical characteristics of the DMB-TH, and introduces the system technical parameters of the DMB-TH. In third chapter, it discusses fully some basic concepts of channel coding and finite field, the Tanner graph related to the LDPC code, and some relevant content about the BCH and LDPC coding theory. In forth chapter, it focuses on how to design the coding of BCH+LDPC, through analysis and research of the channel coding theory and DMB-TH system in the first three chapters. Firstly, it presents the block diagram of whole design of the channel coding system. And then, it is the detailed design of the parts of the system including scrambler module, BCH coding module, interface circuit module and LDPC coding module. In last chapter, based on the design of the system and each part in the forth chapter, it gives out the implementation process of BCH+LDPC coding with FPGA. First, using the simulation software Modelsim, I conduct the simulation of each module, and explain the simulation result and prove it correct. Finally, it's the complement of the FEC encoding in FPGA with Altera Corporation's CYCLONE series EP2C35F484C8.