| Characterized by long transmission distance, serious loss of signal energy attenuation, deep space communication needs excellent error correcting coding technology to ensure the reliability of information transmission. LDPC (Low-Density Parity-Check) codes have been received more and more attention for their outstanding performance in deep space communication. Quasi-Cyclic LDPC codes can be encoded by shift registers which lower the encoding complexities, and the decoders also have low complexities. As a result, they have been one of the schemes in the CCSDS deep space communication standard.In this dissertation, construction of parity-check matrix and decoding for QC-LDPC codes are investigated by theoretical analysis and computer simulation. The main works are summarized as follows:Constructions of parity check matrix based on ARJA codes of QC-LDPC codes are systematically summarized. The encoding algorithms on the basis of shift registers for QC-LDPC codes are also introduced. Then several soft decoding algorithms for LDPC codes, i.e., sum product algorithm and normalized min-sum algorithm are discussed. Furthermore, decoding performance of different factors is analyzed by computer simulation.Based on principles of normalized min sum decoding algorithm, the FPGA implementation method of decoder for QC-LDPC codes are proposed, and all the key modules including CU, CNU, CNU are also introduced in the FPGA design. LDPC decoder hardware design is completed using VHDL language, and feasibility of hardware design is verified.Hardware platform test results indicate that the hardware design of QC-LDPC codes satisfies the index requirements of CCSDS standard and it can be used in the deep space communication. |