Design Of CRC And FFT Data Processing Circuit Based On AMBA Protocol

Fast Fourier Transform(FFT)reduces the computational load by decomposing the long sequence DFT calculation into a short sequence DFT calculation.FFT is widely used in wireless communication,speech recognition,image processing,spectrum analysis and other fields.Cyclical Redundancy Check code(CRC)with its simple algorithm and powerful error detection capability can greatly improve the reliability of the data and is easy to implement.It is the strong error detection capability and high check efficiency that make CRC widely used in digital communications.Using FFT and CRC as peripheral circuits of the MCU can increase its flexibility,and also enhance the performance of the MCU,making the MCU more efficient in some scenarios.Most MCUs on the market today use advanced microcontroller bus structures.Advanced Microcontroller Bus Architecture(AMBA)is an on-chip interconnect bus specification proposed by ARM.The AMBA specification defines an on-chip communication standard when designing high-performance embedded microcontrollers,which is widely used in MCUs.Although most MCUs on the market have CRC operation functions and FFT operation functions,their low efficiency or high power consumption make it difficult to meet some low-power embedded application scenarios.This thesis designs based on the AMBA protocol MCU architecture.The main structure includes: Cortex-M0 core,DMA,bus matrix,FFT,memory,APB bridge,etc.The CRC calculation circuits are designed to optimize the CRC32 calculation in low-power embedded systems.Making the FFT operation away from the MCU core,reducing the operation power consumption and increasing the operation speed.CRC32 calculation adopts parallel calculation method to achieve the purpose of improving the calculation speed.The relationship between CRC32 parallel generator polynomial and calculation result is obtained through matrix simplification.Corresponding hardware circuits are set up for implementation.The DMA dedicated to FFT data handling is used for data transmission,so that the FFT operation data on the CPU bus no longer passes through the CPU bus,and the CPU does not need to be FFT butterfly operation is performed,so the CPU can process other operations or enter sleep mode during the FFT operation,which greatly saves power consumption.This thesis optimizes the 32-bit CRC parallel calculation,thereby effectively solving the problems of low application flexibility and slow calculation speed caused by the previous CRC due to the use of a fixed generator polynomial method or a serial calculation method.The FFT operation circuit designed in this thesis solves the problem that FFT operation needs to occupy a lot of resources in the M0 core.In this paper,the 8-bit parallel operation of the polynomial CRC32 can be implemented to meet the higher frequency,and the FFT coreless operation on the MCU is realized.The FFT operation time is 23041 clock cycles under ideal conditions.The specific innovative content includes the implementation of CRC calculation hardware,the data transfer of FFT operation through DMA,and the butterfly operation of FFT are implemented in the MCU in a modular manner.