A Bcd Process Development And Optimization Of The Power Driver Circuit

This thesis designs a package of process for middle voltage, high current and power applications, which integrate 80V power VDMOS device with less on-resistance. This thesis mainly focus on the on-resistance and current capacity design and optimizing.BCD processes are widely used in analog IC design field since its invention. One kind of the BCD process called high power BCD with middle voltage and high current is applied in auto electronic, drivers etc. Internal BCD process development is limited to high density BCD processes which are always for the applications less than 50V. High power BCD is nearly blank in our country, This will limit the development of microelectronics technology of China. Therefore, developing a package of high power BCD process is very significant.According to an H bridge driver IC's application, we confirmed the electrical parameters of the integrated power VDMOS device. First of all, on the basis of the device's threshold voltage and other parameters, we can predesign structure parameters of the power VDMOS cellular. And on the basis of device on-resistance study, we optimized the main factors of power VDMOS cellular on-resistance, such as poly width and the impurity concentration of epitaxial layer. Then by the device simulation and process device co-simulation, we fixed the conclusion of theoretical analysis, and get the finalization of the process steps of the BCD process and process recipe of each step. Then we focus on the special drain structure of integrated VDMOS device, which is much different to the discrete one. On this basis, we established the single cellular array on-resistance netlist model, and preliminarily optimized the number of cellular which share one drain structure. Meanwhile, the separation parameter cellular model verified the conclusion.According to the above, we run the first experimental lots, and tested the first lots samples. Through the analysis of the test results, further improvement were adopt to fix the integrated power VDMOS device on-resistance model, and further optimized the structure of device in order decrease the on-resistance and increase the current capacity. At last, we run the second experimental lots, and the test results met he original design specifications.