An Fpga Programmable Logic Block Structure And Design

With the rising costs of the mask of the ASIC (application specific integrated circuit), and if there is an error in the process of the design, the risks of market launch must be beared, so the FPGA (field programmable gate array) devices with repeatable programming capability have got in used more and more widely. To make a target of the CLB cell of FPGA, this paper is aim to look for a high-performance realization of it.The method of forward design is used in this paper, the main content of which contains the study of the structure realization of the component module in the CLB unit, a highly efficient and saving circuit resources implementation structure of the CLB unit is proposed, digital and analog simulation is implemented for the verification of various logic functions of CLB, and the its transmission parameters. The results of the simlation and verification ensure the implementation of CLB circuit not only have good characteristics, and also have high coverage of the logic functions it can achieve.Learned from the design method of the related FPGA products of the domestic and the international, focused on the development trend of CLB structure and the main factors which determine the functions and features of CLB, got the rational division of CLB, used the optimal composition which can be achieved under the context of current technology, then the structure composed of optimized components is targeted to get best characteristics. For example, the problem of charge sharing in the traditional structure of LUT circuit is eliminated; in another, a simplified structure of programmable registers is proposed, which can significantly save the circuit area, and ensure the capability of the implementation of basic logic functions and lower path delay.Through layout and verification for the CLB structure, the CLB modules is stitched to achieve the build of a million-gate FPGA chip. Then the functional simulation for the whole FPGA is implemented, to a certain extent, the simulation results ensure the programmable capability and highly efficient implementation for various logic functions of the FPGA chip.